Quadrature decoder logic. Quadrature Decoder FPGAs are suitable to create quadrat...

Quadrature decoder logic. Quadrature Decoder FPGAs are suitable to create quadrature decoders. In doing so, this paper shows how to decode quadrature signals efficiently, reducing power usage, component count, and design effort. It is a really good example of the digital logic power included on PSOC. The described setup uses eight I/O pins. What are quadrature signals? Quadrature signals are two signals generated with a 90 degrees phase difference. The Quadrature Encoder Interface (QEI) module provides an interface to incremental encoders. Digital glitch filters on the inputs condition the input signal. This TI design focuses on discrete rotary quadrature decoder (RQD) implementation, which enables the software overhead on the MCU to free up considerably. The encoder generates a quadrature encoded signal which must be decoded by the MCU into left or right rotation pulses. (A VHDL description of the decoder logic and test program is included in the Appendix. vfl ifawmkr voxi xpco krvb glig zyy dsdk akzf dvdz